The use of global registers as part of the interconnection and control mechanisms for multiprocessor systems is well known in the prior art. Global registers are registers that are generally accessible to all requestors in a multiprocessor system. In an article by E. W. Dijkstra entitled "Co-operating Sequential Processes," in F. Genuys (ed.), Programming Languages (Academic Press, New York 1968), Dijkstra describes the use of global registers for a semaphore operation to control the operational flow of a multiprocessor system. The use of global registers as part of a semaphore operation is typically limited to minimally parallel supercomputers and hierarchical memory supercomputers. Massively parallel supercomputers, by their very architecture, do not have a use for a set of global registers as control and coordination of the processors is accomplished via a message passing scheme.
Most prior art global register systems utilize some form of hardware dependent interlock mechanism to accomplish the semaphore function. For example, in the architecture for the Cray X-MP supercomputer developed by Cray Research, Inc., that is the subject of U.S. Pat. No. 4,636,942, a deadlock interrupt means is used to coordinate requests to the global registers by two high-speed processors. While this type of tightly-coupled, direct-connection method is an efficient means for coordinating two high speed processors, the hardware deadlock interrupt mechanism described in that patent is most effective when both the number of processors being coupled together and the number of global registers involved are relatively small.
In addition, most prior art global register systems have been implemented using a small set of global registers with relatively few access paths. Because minimally parallel supercomputers typically operate with a centralized operating system, many of the potential conflicts for global register usage are controlled by the centralized operating system which can limit the number of processors assigned to access a given global register. As a result, there has generally been no need in the prior art to provide for a large number of global registers capable of distributed and/or multithreaded processing on the contents of more than one global register at a time.
The design of global registers for supercomputers has been problematic in prior art multiprocessor systems, even with the limited design requirements of those architectures. In an effort to increase the processing speed and flexibility of multiprocessor computer processing systems, the previously identified parent application to the present invention, Ser. No. 07/459,083, provides a cluster architecture that allows a number of processors and external interface ports to make multiple and simultaneous requests to a common set of shared hardware resources. One of those shared hardware resources is a set of global registers. The problem of global register design is further compounded by several important design factors that are utilized in the design of this cluster architecture. First, the global registers must be capable of supporting many multiple requests to the same global register. Second, the global registers must operate in a distributed environment where there is no central scheduler and where portions of the distributed input/output are also allowed direct access to the global registers without processor intervention. Finally, the global registers must be capable of atomic arithmetic operations and atomic resource allocation operations in order to support the software routines for a multithreaded operating system that use shared-variable synchronization and anarchy-based scheduling to allocate work and coordinate access to common data structures used by the operating system.
The problem of global register design has generally been managed in prior art supercomputers by assigning a single, central scheduling processor to keep track of what resources were currently being used by which processor. In the distributed access architecture of the cluster architecture for a multiprocessor system, access to all shared resources, including global registers, is equal and democratic and there is no central scheduler. Consequently, a new design for global registers for a distributed access architecture multiprocessor system is needed.